How to Get Involved
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It's never too early to get involved! Based on your objectives, we can create bespoke packages designed specifically for you.
From presenting your expertize on the main stage to hosting the infamous Drinks Reception. You can partner with us showcase your brand and make valuable new connections. Opportunities predominantly lie in 3 main categories: Thought Leadership, Branding & Networking.
Discuss your objectives with Ben Edwards, Commercial Director; [email protected].
Register as a Delegate
MemCon empowers engineers and architects working on memory-constrained problems with peer insights from case studies in genomics, AIML, datacenter, HPC, computational fluid dynamics, in-memory databases, and enterprise knowledge graphs.
Step into interactive discussions and engaging presentations at the first memory event focused on end users and systems.
REGISTER YOUR INTEREST FOR 2024 HERE.
About The Event
MemCon is the first memory event focused on end users and systems.
MemCon empowers engineers and architects working on memory-constrained problems with peer insights from case studies in genomics, AIML, datacenter, HPC, computational fluid dynamics, in-memory databases, and enterprise knowledge graphs. If you are working on a memory-bound problem, come and unpack it with your peers, and get your hands on tech demos at the same time.
For memory systems designers, MemCon is a market deep-dive, a launchpad for CXL and emerging memory products, and a one-stop shop to meet enterprise data experts.
Starting with datacenters and servers in 2023, MemCon will tackle memory-bound use cases in modern and future computing. Working back from the end point – what do future systems need to look like? - the conference will focus on the intersection between systems design, memory innovation (emerging memories, storage & CXL) and other enabling technologies, such as photonics.
- Come and collaborate on solving memory-bound use cases.
- Beat systems bottlenecks with insights from systems architects and memory experts.
- Witness industry-defining emerging memory and CXL product launches.
- Keep your memory product development on target with market feedback.
- Join a network of systems and AIML experts, plus end users.
Event Themes:
Previous Speakers
Tom Garvens
Zaid Kahn
Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.
Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.
Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.
Jinman Han
Jinman Han serves as President of Samsung Device Solutions Americas (DSA) and Corporate EVP of Samsung Electronics, responsible for Samsung's U.S. semiconductor business, which includes Memory, Foundry, System LSI, and LED.
Jinman is a respected leader who has held many leadership positions at Samsung throughout his career, most recently as head of the Memory Global Sales & Marketing team. He joined Samsung in 1989 and has worked in various departments, including DRAM design, Flash design, Flash solution product planning, Memory product planning and application engineering, and SSD development.
His expertise and insight in the industry have contributed significantly to the company's presence within the memory market and have helped maintain Samsung's market leadership for decades.
Jinman is based in San Jose, CA, and holds a bachelor's degree in Electrical Engineering from Seoul National University in Korea.
Jin-Hyeok Choi
Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.
Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.
Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.
Dimitri Kusnezov
Dr. Dimitri Kusnezov [Kooz-NETS-off] was confirmed as the Under Secretary for the Science and Technology Directorate (S&T) on September 8, 2022. As the science advisor to the Homeland Security Secretary, Dr. Kusnezov heads the research, development, innovation and testing and evaluation activities in support of the Department of Homeland Security’s (DHS) operational Components and first responders across the nation. S&T is responsible for identifying operational gaps, conceptualizing art-of-the-possible solutions, and delivering operational results that improve the security and resilience of the nation.
Prior to DHS, Dr. Kusnezov was a theoretical physicist working at the U.S. Department of Energy (DOE) focusing on emerging technologies. He served in numerous positions, including the Deputy Under Secretary for Artificial Intelligence (AI) & Technology where he led efforts to drive AI innovation and bring it into DOE missions, business and operations, including through the creation of a new AI Office.
Dr. Kusnezov has served in scientific and national security positions, including Senior Advisor to the Secretary of Energy, Chief Scientist for the National Nuclear Security Administration, Director of Advanced Simulation and Computing and the Director of the multi-billion-dollar National Security Science, Technology and Engineering programs. He created numerous programs, including for Minority Serving Institutions, international partners, private sector and philanthropic entities. He has worked across agencies to deliver major milestones such as DOE’s 10-year grand challenge for a 100 Teraflop supercomputer, and first of their kind and world’s fastest supercomputers.
Prior to DOE and his pursuit of public service, Dr. Kusnezov had a long career in academia where he published more than 100 articles and edited two books. He joined Yale University faculty where he was a professor for more than a decade in Theoretical Physics and served as a visiting professor at numerous universities around the world. Before this post, Dr. Kusnezov did a brief postdoc and was an instructor at Michigan State University, following a year of research at the Institut fur Kernphysik, KFA-Julich, in Germany. He earned his MS in Physics and Ph.D. in Theoretical Nuclear Physics at Princeton University and received Bachelor of Arts degrees in Physics and in Pure Mathematics with highest honors from UC Berkeley.
Steve Pawlowski
Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.
Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.
Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.
Tom Sheffler
Nick Wright
Nick Wright is the advanced technologies group lead and the NERSC chief architect. He focuses upon evaluating future technologies for potential application in scientific computing. He led the effort to optimize the architecture of the Perlmutter machine, the first NERSC platform designed to meet needs of both large scale simulation and data analysis from experimental facilities. Before moving to NERSC, he was a member of the Performance Modeling and Characterization (PMaC) group at the San Diego Supercomputing Center. He earned both his undergraduate and doctoral degrees in chemistry at the University of Durham in England.
Natalia Vassillieva
Natalia was a Sr. Research Manager at Hewlett Packard Labs, where she led the Software and AI group and served as the head of HP Labs Russia from 2011 until 2015. Prior to HPE, she was an Associate Professor at St. Petersburg State University in Russia and worked as a software engineer for several IT companies. Natalia holds a Ph.D. in computer science from St. Petersburg State University.
Tirthankar Lahiri
Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.
Samir Rajadnya
Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.
Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.
Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.
Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.
Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture
Dan McCreary
Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.
Dirk Van Essendelft
Dr. Van Essendelft is the principle investigator for the integration of AI/ML with scientific simulations within in the Computational Device Engineering Team at the National Energy Technology Laboratory. The focus of Dr. Van Essendelft’s work is building a comprehensive hardware and software ecosystem that maximizes speed, accuracy, and energy efficiency of AI/ML accelerated scientific simulations. Currently, his work centers around building Computational Fluid Dynamics capability within the TensorFlow framework, generating AI/ML based predictors, and ensuring the ecosystem is compatible with the fastest possible accelerators and processors in industry. In this way, Dr. Van Essendelft is developing NETL’s first cognitive-in-the-loop simulation capability in which AI/ML models can be used any point to bring acceleration and/or closures in new ways. Dr. Van Essendelft sits on the Technical Advisory Group for NETL’s new Science-Based Artificial Intelligence/Machine Learning Institute (SAMI) and holds degrees in Energy and Geo-Environmental Engineering, Chemical and Biochemical Engineering, and Chemical Engineering from the Pennsylvania State University, University of California, Irvine, and Calvin College respectively.
Recent publications:
Rocki, K., Van Essendelft, D., Sharapov, I., Schreiber, R., Morrison, M., Kibardin, V., Portnoy, A., Dietiker, J. F., Syamlal, M., and James, M. (2020) Fast stencil-code computation on a wafer-scale processor, In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp pp 1-14, IEEE Press, Atlanta, Georgia.
David Emberson
David Emberson is Senior Distinguished Technologist for HPC System Architecture, where he is working on future memory system designs for HPE Cray systems. He began his career at MIT's Digital Systems Laboratory, where he built one of the first portable computers in 1975. He has held positions at Prime Computer, Megatest, Ametek Computer Research, and Sun Microsystems. At Sun, Mr. Emberson was a member of the SPARC architecture committee, managed the SparcStation 10 and SparcStation 20 programs, and was Senior Director at SunLabs. His consulting clients have included the Hypertransport Consortium, AMD, Intel, Atheros, PathScale, Qlogic and numerous startup companies.
At HPE he was Technical Director of HPE's PathForward program for the Department of Energy's Exascale Computing Program. His current research is in memory system design for HPC systems. He serves on the JEDEC J42.2 (HBM) committee and is a Senior Member of IEEE. Mr. Emberson has a B.S. in Electrical Engineering from MIT. He holds nineteen patents.
Rob Ober
Rob is NVIDIA’s data center Chief Platform Architect, working with Hyperscalers to build GPU clusters for AI and Deep Learning, develop systems and platform architecture, and influence the HW and SW GPU roadmaps at NVIDIA. His interest in AI and DL was driven by its impact on computer science and computer architecture.
With more than 35 years experience, Rob was Senior Fellow of Enterprise Technology at SanDisk / FusionIO, Corporate Fellow and Chief Architect at LSI; Fellow and Architect at AMD; Chief Architect at Infineon; Manager of Technologies at Apple Computer, as well as designer of supercomputers, mainframes, and networks.
Rob has over 40 international patents in processor architecture, storage systems, SSDs, networks, wireless, power management, and mobile devices. He has developed architecture and implementation of CRAY, ARM, PowerPC, ARC, Sparc, TriCore and x86 processors.
Keith Winkeler
Keith Winkeler is VP of Engineering, PowerEdge & Core Compute Platforms at Dell Technologies. Keith is an accomplished and collaborative executive with 30 years of demonstrated excellence in building and leading high performance global organizations responsible for architectural definition, development and delivery of industry leading HW/SW products. His proven strengths include talent management and development, organizational design, matrixed and global teams, ODM partner leadership and value chain management.
Mark Orthodoxou
Mark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Datacenter Products Group. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines, including enterprise storage, data center compute, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip, Microsemi, PMC-Sierra, and IDT.
Jean Bozman
Jean S. Bozman is an IT industry analyst focusing on cloud infrastructure and the proud founder of a new company, Cloud Architects Advisors LLC.
She has had experience as an IDC Research VP for 10+ years and has covered the semiconductor industry as an analyst for over 20 years.
Yang Seok Ki
Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a member of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.
Matthew Burns
Matthew Burns develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years, he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.
Sumti Jairath
Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.
Bill Gervasi
Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.
Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.
Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.
Bill makes the best coffee in the world, in case you wondered.
Ahmad Danesh
Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.
Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.
Shrijeet Mukherjee
Shrijeet is a Co-Founder and the Chief Development Officer of Enfabrica. Prior to founding Enfabrica, he was an architect in Google’s infrastructure group. Previously, he was VP Engineering at Cumulus Networks where he built the industry’s first disaggregated Linux-native network operating system. He was the software engineering leader and architect of the industry’s first virtualization/storage offload “smart-NICs” for Cisco UCS. At SGI he was part of the Advanced Graphics team that pioneered floating point framebuffers and programmable shaders. Shrijeet is on the Linux NetDev Society Board of Directors and has over 20 patents. He holds an MS in Computer Science from the University of Oregon.
Camberley Bates
Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.
Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.
She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.
Tom Coughlin
Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant. He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.
Dr. Coughlin has many publications and six patents to his credit. Tom is also the author of Digital Storage in Consumer Electronics: The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services. Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports. Tom is also a regular contributor on digital storage for Forbes.com and other blogs.
Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations. Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years. He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV). For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.
Mahesh Wagh
Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.
Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.
Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.
Jim Handy
Debendra Das Sharma
Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board
Uri Rosenberg
Uri Rosenberg is the Specialist Technical Manager of AI & ML services within enterprise support at Amazon Web Services (AWS) EMEA. Uri works to empower enterprise customers on all things ML: from underwater computer vision models that monitor fish to training models on satellite images in space; from optimizing costs to strategic discussions on deep learning and ethics. Uri brings his extensive experience to drive success of customers at all stages of ML adoption.
Before AWS, Uri led the ML projects at AT&T innovation center in Israel, working on deep learning models with extreme security and privacy constraints.
Uri is also an AWS certified Lead Machine learning subject matter expert and holds an MsC in Computer Science from Tel-Aviv Academic College, where his research focused on large scale deep learning models.
Pedram Khalili
Pedram Khalili-Amiri works on developing the computing systems of the future, starting from novel nano-scale devices/materials that enable systems with unprecedented performance and energy efficiency. Much of his work involves devices that use both the spin and charge of electrons, also referred to as spintronics. Previously Pedram was an adjunct assistant professor in the department of electrical and computer engineering at UCLA from 2013-2017, where he co-led the memory program within the NSF TANMS center, focusing on development of electric-field-controlled magnetic memory with unprecedented energy efficiency. During 2009-2014, at UCLA he was project manager of two DARPA multi-institution programs, focusing on the development of spin-transfer-torque magnetic random access memory (STT-MRAM) and non-volatile logic (NVL), working with several major industry and university partners. These programs resulted in the world’s fastest and lowest-power magnetic memory technologies at the time. In addition, since 2012 he has been co-founder of Inston Inc., a startup company pioneering voltage-controlled MRAM for high-performance computing applications, where he also served as board member and chief technology officer for five years. His professional activities have included serving as a guest editor for Spin, and serving on the technical program committee of the Joint MMM/Intermag Conference.
Simone Bertolazzi
Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architectures and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.
Arvind Jagannath
Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.
David McIntyre
Seong Kim
As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.
Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.
Seungwon Lee
Seungwon Lee is a Master (VP of Technology) at Samsung, where he leads Computing SW Team at SAIT(Samsung Advanced Institute of Technology) of Samsung Electronics.
His research interests include large scale deep learning computing SW and In/Near memory computing SW.
Lee received a Ph.D degree in computer science and engineering from Seoul National University.
Arthur Sainio
Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.
As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.
Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.
Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.
Keith McKay
Andy Mills
Andy Mills is the Snr Director of Advanced Product Development at SMART Modular Technologies, where he leads the development of next generation CXL memory and data center storage solutions.
Prior to joining SMART, Andy was CEO/co-founder of Enmotus, Inc where he co-developed and led the development of intelligent storage and memory tiering solutions for data center and high end PCs utilizing advanced learning algorithms driven by real time intelligent workload analysis. He has more than 30 years industry experience in software development, systems architecture, networking, storage and semiconductor development, plus held various management and technical lead positions at DotHill Systems, NetCell Corporation, TDK Semi, AMD.
Andy graduated with an MEng and BEng with Honors from Bangor University in the UK.
Seyong Lee
Seyong Lee is a Senior R&D Staff in the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL). His research interests include parallel programming and performance optimization in heterogeneous computing environments, program analysis, and optimizing compilers. He received his PhD in Electrical and Computer Engineering from Purdue University, USA.
He is a member of the OpenACC Technical Committee and a former member of the Seed Review Committee of the ORNL Seed Program and the NVIDIA PathForward Working Group of the Exascale Computing Project PathForward Program.
He served as a program committee/guest editor/external reviewer for various conferences, journals, and research proposals.
His paper on SC10 won the best student paper award, and his paper on PPoPP09 was selected as the most cited paper among all papers published in PPoPP between 2009 and 2014.
He received the IEEE Computer Society TCHPC Award for Excellence for Early Career Researchers in High Performance Computing at SC16 and served as an award committee member for 2017 IEEE CS TCHPC Award.
See his website for more information: https://seyonglee.github.io.
Paul Crumley
Paul G Crumley, a Senior Technical Staff Member at IBM Research, enjoys creating systems to solve problems beyond the reach of current technology.
Paul’s current project integrates secure, compliant AI capabilities with enterprise Hybrid Cloud allowing clients to extract new business value from their data.
Paul’s previous work includes the design and construction of distributed, and high-performance computing systems at CMU, Transarc, and IBM Research. Projects include The Andrew Project at CMU, ASCI White, IBM Global Storage Architecture, Blue Gene Supercomputers, IBM Cloud, and IBM Cognitive Systems. Paul has managed data centers, and brings his first-hand knowledge of these environments, combined with experience of automation and robustness, to the design of AI for Hybrid Cloud infrastructure.
Nuwan Jayasena
Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.
George Apostol
George has over 35 years of experience designing system-on-chip (SoC), hardware, software, and systems. He holds several patents for interconnect and interface design and has led technology organizations developing products for several markets. He has held leadership and executive roles at Xerox/PARC, Sun, SGI, LSI Logic, Exar, and Samsung as well as start-ups including TiVo, BRECIS, Audience and BAYIS. As VP of Engineering and CTO at PLX Technology, George drove the development of PCI Express switches, which are broadly used in the market today. He received his bachelor’s degree in Electrical Engineering from the Massachusetts Institute of Technology.
Stephen Bates
Stephen is a VP and the Chief Architect of Emerging Storage Systems at Huawei. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.. Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE. He is a member of the SNIA Technical Council.
Venkatram Vishwanath
Venkatram Vishwanath is a computer scientist at Argonne National Laboratory. He is the Data Science Team Lead at the Argonne leadership computing facility (ALCF). His current focus is on algorithms, system software, and workflows to facilitate data-centric applications on supercomputing systems. His interests include scientific applications, supercomputing architectures, parallel algorithms and runtimes, scalable analytics and collaborative workspaces. He has received best papers awards at venues including HPDC and LDAV, and a Gordon Bell finalist. Vishwanath received his Ph.D. in computer science from the University of Illinois at Chicago in 2009.
Research Interests
- Scientific data analysis and visualization
- Parallel I/O and I/O middleware
- Large-scale computing systems and other exotic architectures (Blue Gene, Cray, multi-core systems, GPUs and other accelerators)
- High-speed interconnects (InfiniBand, high-speed Ethernet, optical), data movement and transfer protocols, and (v) collaboration workspaces
Jongryool Kim
Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.
In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.
Siamak Tavallaei
Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management. In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack). His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.
PREVIOUS ATTENDEES INCLUDE
On Demand Webinar
Watch our pre-event webinar on demand which will arm you with a primer on the main trends in memory innovation and CXL, show you how Samsung and Roche are overcoming memory bottlenecks, and convince you why you should attend the first ever MemCon in Silicon Valley on March 28-29. Short and sweet!
Previous Partners
Previous Founding Partner
Samsung
Website: www.samsung.com
Samsung Semiconductor, Inc.
Based in the heart of Silicon Valley, Samsung Semiconductor, Inc., is an industry-leading, multi-billion dollar subsidiary of Samsung Electronics Corporation that provides the world’s most advanced technology for consumer electronic devices and computing platforms. Samsung’s state-of-the-art memory, logic, solid state drives, LED components, OLED displays, and foundry services are integrated across AI, high-performance computing, data centers, IoT, automotive and emerging markets. Driven by excellence and innovation, Samsung leverages its proven expertise and leadership to develop technology products that will shape and enhance the consumer’s future.
Previous Gold Partners
Rambus
Website: https://www.rambus.com/
Rambus is a provider of industry-leading chips and silicon IP making data faster and safer. With over 30 years of advanced semiconductor experience, we are a pioneer in high-performance memory subsystems that solve the bottleneck between memory and processing for data-intensive systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data throughput and integrity. Rambus products and innovations deliver the increased bandwidth, capacity and security required to meet the world’s data needs and drive ever-greater end-user experiences. For more information, visit rambus.com.
Samtec
Website: http://www.samtec.com
Founded in 1976, Samtec is a privately held, $822 MM global manufacturer of a broad line of electronic interconnect solutions, including High-Speed Board-to-Board, High-Speed Cables, Mid-Board and Panel Optics, Precision RF, Flexible Stacking, and Micro/Rugged components and cables. With 40+ location severing approximately 125 countries, Samtec’s global presence enables its unmatched customer service.
Previous Event Partners
Astera Labs
Website: https://www.asteralabs.com/
Astera Labs Inc. is a leader in purpose-built data and memory connectivity solutions to remove performance bottlenecks throughout the data center. With locations worldwide, the company’s silicon, software, and system-level connectivity solutions help realize the vision of Artificial Intelligence and Machine Learning in the Cloud through CXL™, PCIe®, and Ethernet technologies.
For more information about Astera Labs including open positions, visit www.AsteraLabs.com.
FuturePlus Systems
Website: https://www.futureplus.com/
Please visit our website for more information.Previous Exhibitor
Previous Association Partners
CXL Consortium
Website: https://www.computeexpresslink.org/
Please visit our website for more information.SNIA
Website: https://www.snia.org/
The Storage Networking Industry Association (SNIA) is pleased to be an association sponsor of MemCon. SNIA is a not-for-profit global organization made up of member companies spanning the storage market. As a recognized and trusted authority for storage leadership, standards, and technology expertise worldwide, SNIA’s mission is to lead the storage industry in developing and promoting vendor-neutral architectures, standards, and educational services that facilitate the efficient management, movement, and security of information. Learn more at www.snia.org
Previous Media Partners
Data Centre Magazine
Website: https://bit.ly/3CTbIoE
Data Centre Magazine is a digital media platform for you to showcase products, expertise, learnings, and achievements with the world’s largest community of data executives. Because, as Robert Noyce famously said, "Knowledge is power. Knowledge shared is power multiplied.” Do this through digital media such as interviews, articles, case studies and videos.
HPCwire
Website: https://www.hpcwire.com/
HPCwire is the #1 news and information resource covering the fastest computers in the world and the people who run them. With a legacy dating back to 1987, HPC has enjoyed more than three decades of world-class editorial and topnotch journalism, making it the portal of choice selected by science, technology and business professionals interested in HPC, AI and data-intensive computing. For topics ranging from late-breaking news and emerging technologies in HPC, to new trends, expert analysis, and exclusive features, HPCwire delivers it all and remains the HPC community’s most reliable and trusted resource. Visit www.hpcwire.com.
InsideHPC
Website: https://insidehpc.com/
Founded in 2006, insideHPC is globally recognized for its thorough and insightful coverage across the HPC community, providing a bridge linking readers among vendors, users and HPC strategists with a following that includes public and private companies of all sizes, government agencies, research centers, industry analysts and academic institutions. In short: the buyers and influencers of HPC, HPC-AI and associated emerging technologies.
THE News Analysis Site for HPC Insiders. We’re all about HPC, but like the emerging HPC ecosystem, insideHPC is evolving with a number of important updates and topic focus areas coming later in 2022. To better serve our growing readership and advertising base, insideHPC will deliver an updated format and featured spotlight coverage of the emerging markets of enterprise HPC, HPC-AI, exascale (and post-exascale) supercomputing, quantum computing, cloud HPC, edge computing and High Performance Data Analytics. Our mission is to cover every aspect of HPC.
Written and edited by seasoned HPC journalists, insideHPC represents the many voices of the global HPC community: where HPC is today and where it’s going.
Khronos Group
Website: https://www.khronos.org/
The Khronos Group is an open, non-profit, member-driven consortium of over 150 industry-leading companies creating advanced, royalty-free interoperability standards for 3D graphics, augmented and virtual reality, parallel programming, vision acceleration and machine learning. Khronos standards include Vulkan®, Vulkan® SC, OpenGL®, OpenGL® ES, OpenGL® SC, WebGL™, SPIR-V™, OpenCL™, SYCL™, OpenVX™, NNEF™, OpenXR™, 3D Commerce™, ANARI™, and glTF™. Khronos members are enabled to contribute to the development of Khronos specifications, are empowered to vote at various stages before public deployment and are able to accelerate the delivery of their cutting-edge accelerated platforms and applications through early access to specification drafts and conformance tests.
Laser Focus World
Website: https://www.laserfocusworld.com/
Please visit our website for more information.Semiconductor Engineering
Website: https://semiengineering.com/
Please visit our website for more information.Tanis Communications
If you're interested in joining MemCon 2023 as a member of the press, please contact [email protected]
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Check out the 2023 post-show report to learn more about the highlights including key takeaways, attendee breakdown, audience feedback and the plans for 2024!
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