Software Eng. | Kisaco Research

Software Eng.

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•        Computational Storage and Memory

•        CXL and UCIe 

•        Emerging Persistent Memory Types 

•        Bridging to the Application Layer 

Use Case
Embedded Memory
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Tom Coughlin

President
Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant.  He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit.  Tom is also the author of Digital Storage in Consumer Electronics:  The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services.  Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports.  Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations.  Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years.  He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV).  For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

Tom Coughlin

President
Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant.  He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit.  Tom is also the author of Digital Storage in Consumer Electronics:  The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services.  Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports.  Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations.  Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years.  He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV).  For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

Author:

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Author:

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Author:

Arthur Sainio

Director, Product Marketing
Smart Modular Technologies

Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.

As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.

Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.

Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.

Arthur Sainio

Director, Product Marketing
Smart Modular Technologies

Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.

As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.

Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.

Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.

CPU performance improvement based on Dennard scaling and Moore's Law has already reached its limit, and domain-specific computing was considered as an alternative to overcome the limitations of the existing CPU-centric computing model. Domain-specific computing, seen in early graphics and network cards, has expanded into accelerators such as GPGPUS, TPUs, FPGAS, and IDPs. Meanwhile, hyperscalers, where power efficiency is particularly important, use ASICs or FPGAs to offload and accelerate OS, security, and data processing tasks. Handling large amounts of data in a power-efficient manner requires reexamining the model for moving data from traditional storage to the CPU. This model consumes a lot of power and limits performance due to bandwidth limitations. Computer Storage (CS) or In-Storage Computing (ISC), first explored in the 1990s, is another important piece of the puzzle. As data is explosively generated in the cloud, machine learning, big data, and edge, the industry is actively reviewing the application of CS in various fields. This panel discusses the current state of CS, its potentials and challenges in various applications.

Emerging Memories
Embedded Memory
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Yang Seok Ki

VP & CTO, Memory Solutions Lab
Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a member of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

Yang Seok Ki

VP & CTO, Memory Solutions Lab
Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a member of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

Panellists

Author:

Stephen Bates

VP & Chief Architect, Emerging Storage Systems
Huawei

Stephen is the VP and  Chief Architect of Emerging Storage Systems at Huawei's Toronto Emerging Storage Lab. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. He is also very active in both the SNIA and NVM Express standard bodies.

Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. He was also formerly in the CTO office at PMC-Sierra, an Assistant Professor at The Univeristy of Alberta and a Principal Engineer at Massana Inc. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Stephen Bates

VP & Chief Architect, Emerging Storage Systems
Huawei

Stephen is the VP and  Chief Architect of Emerging Storage Systems at Huawei's Toronto Emerging Storage Lab. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. He is also very active in both the SNIA and NVM Express standard bodies.

Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. He was also formerly in the CTO office at PMC-Sierra, an Assistant Professor at The Univeristy of Alberta and a Principal Engineer at Massana Inc. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Author:

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Author:

Seong Kim

Senior Director, Datacenter Solutions Architect
AMD

As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.

 

Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.

Seong Kim

Senior Director, Datacenter Solutions Architect
AMD

As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.

 

Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.

Author:

Keith McKay

Senior Director
ScaleFlux

Keith McKay

Senior Director
ScaleFlux

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

Author:

Jongryool Kim

Research Director
SK Hynix

Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.

In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.

Jongryool Kim

Research Director
SK Hynix

Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.

In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.

Embedded Memory
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Jin-Hyeok Choi

Corporate EVP, Device Solution Research America - Memory
Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

Jin-Hyeok Choi

Corporate EVP, Device Solution Research America - Memory
Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

Over the last two decades, large HPC machine efforts have become a procurement exercise.  A large set of applications have been unable to leverage the additional computational power of newly-procured machines without significant additional software development.  The machine architectures need to evolve:  new systems architectures and innovations require a deep understanding of application uses cases and their needs.   Memory and storage, as foundational elements, will be at the center of future innovative systems, driving both greater performance and increased energy efficiency.

CXL
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Steve Pawlowski

CVP, Advanced Memory Systems
Micron

Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.

Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.

Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.

Steve Pawlowski

CVP, Advanced Memory Systems
Micron

Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.

Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.

Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.

CXL
Emerging Memories
External Memory
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Panellists

Author:

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Author:

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Author:

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Author:

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Author:

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

Enterprise knowledge graphs (EKGs) offer the ability to store large connected datasets in memory for fast traversal using simple pointer-hopping instructions.  However, keeping hundreds or thousands of cores feed with traversal data has become one of the key challenges for artificial intelligence and analytics.  Despite the exponential growth in graphs databases we have yet to see hardware tuned to graph analytics workloads.  In this session we will review the requirements for EKGs and provide a roadmap of how new memory hardware can be used to solve EKG challenges.

Embedded Memory
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

With current trends in DRAM capacities and costs, in-memory database technology is rapidly becoming mainstream. Oracle Database In-Memory features a unique dual-format in-memory architecture designed to optimize the performance of simultaneous analytic and transactional workloads on the same data. In addition, the in-memory columnar technology for Oracle Database In-Memory is also available within the storage tier of the Exadata database machine, allowing for effective in-memory columnar capacities to approach 100s of Terabytes.  In-memory processing is more than simply about speed; it enables a fundamental transformation in business processes. Just as air travel enabled more than faster travel - it fundamentally changed society, Oracle Database In-Memory similarly enables not just faster analytics and transactions, but a fundamental rethinking and drastic simplification of the traditional analytic architectures. In this session we will show how, especially when combined with Oracle's many converged database capabilities, Database In-Memory allows for the development of a new class of real-time enterprise applications, with significant reduction in cost and complexity, while providing unmatched performance across a wide range of workloads.

Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Tirthankar Lahiri

SVP, Data & In-Memory Technologies
Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

Tirthankar Lahiri

SVP, Data & In-Memory Technologies
Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

As the cost of sequencing drops and the quantity of data produced by sequencing grows, the amount of processing dedicated to genomics is increasing at a rapid pace.  Genomics is evolving in a number of directions simultaneously.  Some key applications scale naturally to use resources available in the cloud, while other computations benefit from on-prem acceleration using FPGAs or GPUs.  All of these computations strain the bandwidth and capacity of available resources.  In this talk, Roche´s Tom Sheffler will share an overview of the memory-bound challenges present in genomics and venture some possible solutions.

External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Tom Sheffler

Solution Architect, Next Generation Sequencing
Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models.  His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth.  Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data.  He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms.  Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

Tom Sheffler

Solution Architect, Next Generation Sequencing
Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models.  His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth.  Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data.  He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms.  Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

Recent work by the National Energy Technology Laboratory and Cerebras Systems Inc, has underscored the critical needs of sufficient bandwidth and latency in scientific computing.  In this work, the team demonstrated (to the best of our knowledge) the fastest solution to field equations in computing history.  These remarkable results were made possible by the trifecta of great memory bandwidth, great interconnect bandwidth, and amazing (one clock cycle) communication latency and injection rate for small messages.  Furthermore, the bandwidths are sufficiently high such that no memory hierarchy is necessary which significantly simplifies programming models and software development effort and expense.  In this talk we will outline the conditions necessary to achieve these results.

Embedded Memory
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Dirk Van Essendelft

HPC & AI Architect
National Energy Technology Laboratory

Dr. Van Essendelft is the principle investigator for the integration of AI/ML with scientific simulations within in the Computational Device Engineering Team at the National Energy Technology Laboratory.  The focus of Dr. Van Essendelft’s work is building a comprehensive hardware and software ecosystem that maximizes speed, accuracy, and energy efficiency of AI/ML accelerated scientific simulations.  Currently, his work centers around building Computational Fluid Dynamics capability within the TensorFlow framework, generating AI/ML based predictors, and ensuring the ecosystem is compatible with the fastest possible accelerators and processors in industry.  In this way, Dr. Van Essendelft is developing NETL’s first cognitive-in-the-loop simulation capability in which AI/ML models can be used any point to bring acceleration and/or closures in new ways.  Dr. Van Essendelft sits on the Technical Advisory Group for NETL’s new Science-Based Artificial Intelligence/Machine Learning Institute (SAMI) and holds degrees in Energy and Geo-Environmental Engineering, Chemical and Biochemical Engineering, and Chemical Engineering from the Pennsylvania State University, University of California, Irvine, and Calvin College respectively.

Recent publications:

  • Rocki, K., Van Essendelft, D., Sharapov, I., Schreiber, R., Morrison, M., Kibardin, V., Portnoy, A., Dietiker, J. F., Syamlal, M., and James, M. (2020) Fast stencil-code computation on a wafer-scale processor, In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp pp 1-14, IEEE Press, Atlanta, Georgia.

Dirk Van Essendelft

HPC & AI Architect
National Energy Technology Laboratory

Dr. Van Essendelft is the principle investigator for the integration of AI/ML with scientific simulations within in the Computational Device Engineering Team at the National Energy Technology Laboratory.  The focus of Dr. Van Essendelft’s work is building a comprehensive hardware and software ecosystem that maximizes speed, accuracy, and energy efficiency of AI/ML accelerated scientific simulations.  Currently, his work centers around building Computational Fluid Dynamics capability within the TensorFlow framework, generating AI/ML based predictors, and ensuring the ecosystem is compatible with the fastest possible accelerators and processors in industry.  In this way, Dr. Van Essendelft is developing NETL’s first cognitive-in-the-loop simulation capability in which AI/ML models can be used any point to bring acceleration and/or closures in new ways.  Dr. Van Essendelft sits on the Technical Advisory Group for NETL’s new Science-Based Artificial Intelligence/Machine Learning Institute (SAMI) and holds degrees in Energy and Geo-Environmental Engineering, Chemical and Biochemical Engineering, and Chemical Engineering from the Pennsylvania State University, University of California, Irvine, and Calvin College respectively.

Recent publications:

  • Rocki, K., Van Essendelft, D., Sharapov, I., Schreiber, R., Morrison, M., Kibardin, V., Portnoy, A., Dietiker, J. F., Syamlal, M., and James, M. (2020) Fast stencil-code computation on a wafer-scale processor, In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp pp 1-14, IEEE Press, Atlanta, Georgia.